Principal Static Timing Analysis (STA) Engineer
Microsoft s custom silicon design team is developing some of the highest performance, most ambitious chips in the industry.
The Physical Design team is looking for Principal Static Timing Analysis (STA) Engineer to join us as we continue to build a world-class team and methodology.
Our responsibilities span the complete spectrum including Design for Testability (DFT), fullRegister Transfer Level (RTL) design (GDS)Graphic Data Stream (RTL2GDS), and signoff.
If you are a highly motivated self-starter who has the skills to make an impact in this environment, we d love to hear from you!Required/Minimum Qualifications9
years of related technical engineering experience o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6
years technical engineering experience or internship experience o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4
years technical engineering experience or internship experience o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3
years technical engineering experience.
5
Experience in tapeouts of complex Application Specific Integrated Circuits (ASICs) in leading edge technologyOther Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include, but are not limited to, the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred
Qualifications:
Strong expertise in extraction and STA plus or more of the following:
synthesis, floorplanning, placement, clock/power grid construction, routing, low power methodologies, and other signoff steps (Formal Verification (FV), Low power verification (LPV), Extraction, EMIR, Physical Verification, Power Analysis)Strong scripting skillsProven experience in closing and signing off timing on complex hierarchical chips in advanced process nodesGood understanding of foundry tech files and rule decksSilicon Engineering IC5 - The typical base pay range for this role across the U.
S.
is USD $133,600 - $256,800 per year.
There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.
Certain roles may be eligible for benefits and other compensation.
Find additional benefits and pay information here:
Microsoft is an equal opportunity employer.
All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.
If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
As a Principal Static Timing Analysis (STA) Engineer, you will be responsible for closing timing at block, sub-chip, and/or full-chip level.
The tasks will include setup, hold, transition, max_cap, min_period, min_pulse_width, noise, double switching, skew, and other timing quality checks.
You may also be involved in extraction and STA flow development/automation, convergence strategies/methodologies, correlation Place and route (PNR) to STA, Spice to STA, silicon to STA, constraints, margining, corner selection, and advising the Physical Design team on implementation best practices.
You will work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team.
Occasional travel may be required.
Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering.
Estimated Salary: $20 to $28 per hour based on qualifications.
The Physical Design team is looking for Principal Static Timing Analysis (STA) Engineer to join us as we continue to build a world-class team and methodology.
Our responsibilities span the complete spectrum including Design for Testability (DFT), fullRegister Transfer Level (RTL) design (GDS)Graphic Data Stream (RTL2GDS), and signoff.
If you are a highly motivated self-starter who has the skills to make an impact in this environment, we d love to hear from you!Required/Minimum Qualifications9
years of related technical engineering experience o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6
years technical engineering experience or internship experience o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4
years technical engineering experience or internship experience o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3
years technical engineering experience.
5
Experience in tapeouts of complex Application Specific Integrated Circuits (ASICs) in leading edge technologyOther Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include, but are not limited to, the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred
Qualifications:
Strong expertise in extraction and STA plus or more of the following:
synthesis, floorplanning, placement, clock/power grid construction, routing, low power methodologies, and other signoff steps (Formal Verification (FV), Low power verification (LPV), Extraction, EMIR, Physical Verification, Power Analysis)Strong scripting skillsProven experience in closing and signing off timing on complex hierarchical chips in advanced process nodesGood understanding of foundry tech files and rule decksSilicon Engineering IC5 - The typical base pay range for this role across the U.
S.
is USD $133,600 - $256,800 per year.
There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.
Certain roles may be eligible for benefits and other compensation.
Find additional benefits and pay information here:
Microsoft is an equal opportunity employer.
All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.
If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
As a Principal Static Timing Analysis (STA) Engineer, you will be responsible for closing timing at block, sub-chip, and/or full-chip level.
The tasks will include setup, hold, transition, max_cap, min_period, min_pulse_width, noise, double switching, skew, and other timing quality checks.
You may also be involved in extraction and STA flow development/automation, convergence strategies/methodologies, correlation Place and route (PNR) to STA, Spice to STA, silicon to STA, constraints, margining, corner selection, and advising the Physical Design team on implementation best practices.
You will work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team.
Occasional travel may be required.
Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering.
Estimated Salary: $20 to $28 per hour based on qualifications.
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